This application is based upon and claims the benefit of priority from prior Japanese Patent Applications P2000-331407 and P2001-324141 filed on Oct. 30, 2000 and Oct. 22, 2001; the entire contents of which are incorporated by reference herein.
The present invention relates to a semiconductor device having trench-type isolation regions, a floating gate, and a control gate. More particularly, the present invention relates to capacitive coupling between a floating gate and a control gate.
A nonvolatile semiconductor storage device is composed of nonvolatile memory cells. These nonvolatile memory cells each have a floating gate and a control gate. Potential of the floating gate is controlled by capacitive coupling between the floating gate and the control gate. As the capacitive coupling between the control gate and the floating gate increases, the voltage of the control gate can be lowered. In order to increase the capacitive coupling, the area where the control gate is proximal to the floating gate is increased as follows. The floating gate has a two-layered structure made of a polycrystalline silicon (Si) film in the first layer and polycrystalline silicon at a second layer. The polycrystalline silicon film of the first layer is formed by self-alignment with trench-type isolation regions. The polycrystalline silicon film of the second layer is formed onto the polycrystalline silicon film of the first layer and the trench type isolation regions. An insulation film is formed onto the polycrystalline silicon of the second layer. A control gate is formed onto this insulation film.
However, this cell structure requires a space, an isolation width xe2x80x9cWtxe2x80x9d of the memory cell, for separating the polycrystalline silicon of the second layers. In addition, this cell structure requires a space, as an alignment margin, during lithography steps.
In this cell structure, in order to increase the capacitive coupling between the floating gate and the control gate, it is effective to increase the film thickness of the floating gate. When the film thickness of the floating gate is increased, capacitive coupling C2 in the floating gate between cells increases. When the capacitive coupling C2 increases, the cell threshold voltage is susceptible to modulation corresponding to the state of data in adjacent cells.
A semiconductor device in accordance with embodiments of the present invention includes a semiconductor substrate including plural trenches on a surface, first and second insulators placed in the trench and upper portions of side faces of the first and second insulators are higher than the surface of the substrate, a third insulation film disposed on the surface of the substrate, one end of the third insulation film contacts with the first insulator, and the other end of the third insulation film contacts with the second insulator, a first conductor disposed on a surface of the third insulation film, one end face of the first conductor contacts with the first insulator, and the other end face of the first conductor contacts with the second insulator, a second conductor disposed at a vicinity of the one end face of the first conductor, a third conductor disposed at a vicinity of the other end face of the first conductor, a fourth insulation film contacting with a first side face of the second conductor and a second side face of the third conductor and contacting with a top face of the first conductor, and a fourth conductor disposed on the fourth insulation film.